1. Field of the Invention
The present invention relates generally to a multi-user memory for digital data.
2. Description of the Related Art
Multi-user memories are being increasingly used to buffer network traffic in router and switching applications. Other applications involving digital data also benefit from the use of multi-user memories. As the number of users of a multi-user memory increases, however, a port address multiplexing logic necessary to connect the increased number of users to the multi-user memory becomes more complex. This increase in complexity acts as a limiting factor for both the speed of the multi-user memory and the number of users that can be achieved in an actual implementation of the multi-user memory.
A conventional multi-user memory receives an address signal directly from an address multiplexer. The address multiplexer receives a number of address inputs representing different address signals to be supplied to the multi-user memory. The address multiplexer also receives a selector signal input to indicate which of the number of address inputs will be passed through an output of the address multiplexer to the multi-user memory. For a number of users to share the multi-user memory, the number of inputs received by the address multiplexer must be equal to the number of users. Thus, with more than just a few users sharing the multi-user memory, the address multiplexer can become large and complex.
There are disadvantages associated with having a large and complex address multiplexer. For example, the large and complex address multiplexer requires more hardware and data path signal routing space when implemented in a CMOS process. Also, the large and complex address multiplexer operates slowly. Such slow operation can necessitate a limiting of a clock rate of a system containing the address multiplexer and multi-user memory. Consequently, limiting of the clock rate adversely affects overall performance of the system.
In view of the foregoing, there is a need for a device, and associated method of operation, that allows multiple users to be efficiently connected to a multi-user memory.